Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes a capacitor including a lower electrode an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3 where ‘A’ is a first metal element and ‘B’ is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO3 where ‘C’ is a third metal element and ‘D’ is a fourth metal element. The lower electrode includes a first layer and a second layer which are alternately and repeatedly stacked. The first layer includes the first metal element and oxygen. The second layer includes the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface the first contact surface corresponding to the second layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application is a continuation of U.S.application Ser. No. 17/034,181, filed on Sep. 28, 2020, which claimspriority under 35 U.S.C. § 119 to Korean Patent Application No.10-2019-0174171, filed on Dec. 24, 2019, in the Korean IntellectualProperty Office, the disclosure of each of which is hereby incorporatedby reference in its entirety.

BACKGROUND

Some example embodiments relate to a semiconductor and, moreparticularly, to a semiconductor device and/or a method of manufacturingthe same.

Semiconductor devices are widely used in an electronic industry becauseof their small sizes, multi-functional characteristics, and/or lowmanufacturing costs. Semiconductor devices have been highly integratedwith the development of the electronic industry. Widths of patternsincluded in semiconductor devices have been reduced to increase theintegration density of semiconductor devices. In particular, as a designrule of a semiconductor memory device such as dynamic random accessmemory (DRAM) is being reduced, a range of capacitance, e.g. a standarddeviation and/or an inter-quartile range and/or a difference between amaximum value and a minimum value of a capacitance, may be increased byoxidation of a lower electrode of a capacitor. Thus, there is desire fora structure of a semiconductor memory device and a method which arecapable of reducing the difference of the capacitance.

SUMMARY

Some example embodiments of inventive concepts may provide asemiconductor device capable of reducing a leakage current of acapacitor and/or a method of manufacturing the same.

Alternatively or additionally, some example embodiments of inventiveconcepts may also provide a semiconductor device capable of improvingreliability and/or a method of manufacturing the same.

According to some example embodiments, a semiconductor device mayinclude a capacitor including a lower electrode an upper electrode, anda dielectric layer between the lower electrode and the upper electrode.The lower electrode includes ABO₃ where ‘A’ is a first metal element and‘B’ is a second metal element having a work function greater than thatof the first metal element. The dielectric layer includes CDO₃ where ‘C’is a third metal element and ‘D’ is a fourth metal element. The lowerelectrode includes a first layer and a second layer which arealternately and repeatedly stacked. The first layer includes the firstmetal element and oxygen. The second layer includes the second metalelement and oxygen. The dielectric layer is in contact with the lowerelectrode at a first contact surface the first contact surfacecorresponding to the second layer.

According to some example embodiments, a semiconductor device mayinclude a capacitor including a lower electrode, an upper electrode, anda dielectric layer between the lower electrode and the upper electrode.The lower electrode includes a first metal element, a second metalelement, and oxygen. The dielectric layer includes a third metalelement, a fourth metal element, and oxygen. The lower electrodeincludes a first layer and a second layer which are alternately andrepeatedly stacked; the first layer includes the first metal element andoxygen. The second layer includes the second metal element and oxygen.The first metal element is at least one of Sr, Ba, La, or Ca, and thesecond metal element is at least one of Ru, Mo, Ir, Co, or Ni. Thedielectric layer contacts the lower electrode at a first contactsurface, the first contact surface corresponding to the second layer.

According to some example embodiments, a semiconductor device mayinclude a first conductive line buried in an upper portion of asubstrate, the first conductive line extending in a first direction, anactive portion in the upper portion of the substrate, the active portiondefined by a device isolation pattern, the active portion including afirst dopant region and a second dopant region which are separated fromeach other with the first conductive line interposed between the firstdopant region and the second dopant region, a second conductive line onthe substrate, the second conductive line extending in a seconddirection intersecting the first direction, the second conductive lineconnected to the first dopant region, a contact connected to the seconddopant region, and a capacitor connected to the second dopant regionthrough the contact. The capacitor includes a lower electrode, an upperelectrode, and a dielectric layer between the lower electrode and theupper electrode. The lower electrode includes ABO₃ where ‘A’ is a firstmetal element and ‘B’ is a second metal element having a work functiongreater than that of the first metal element, the dielectric layerincludes CDO₃ where ‘C’ is a third metal element and ‘D’ is a fourthmetal element. The lower electrode includes a first layer and a secondlayer which are alternately and repeatedly stacked, the first layerincludes the first metal element and oxygen the second layer includesthe second metal element and oxygen. The dielectric layer contacts thelower electrode at a first contact surface of the lower electrode, thefirst surface corresponding to the second layer.

According to some example embodiments, a method of manufacturing asemiconductor device may include forming a lower electrode on asubstrate, forming a dielectric layer on the lower electrode; andforming an upper electrode on the dielectric layer. The forming of thelower electrode comprises performing a lower electrode-forming cycle aplurality of times, and the lower electrode-forming cycle comprises aprocess of depositing a first layer and a process of depositing a secondlayer. The process of depositing the first layer includes supplying afirst metal element source, and supplying an oxygen source. The processof depositing the second layer includes supplying a second metal elementsource, and supplying the oxygen source. The process of depositing thesecond layer ends the forming of the lower electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIG. 1 is a cross-sectional view illustrating a capacitor according tosome example embodiments of inventive concepts.

FIG. 2 is an enlarged view of a region ‘Q’ of FIG. 1 .

FIG. 3 is a plan view of a first layer.

FIG. 4 is a plan view of a second layer.

FIG. 5 is a plan view of a third layer.

FIG. 6 is a plan view of a fourth layer.

FIG. 7 is a conceptual view illustrating an interface between a lowerelectrode and a dielectric layer according to a comparative example.

FIG. 8 is a process flowchart illustrating a method of forming acapacitor, according to some example embodiments of inventive concepts.

FIG. 9 is a conceptual view illustrating a deposition apparatus forforming layers according to some example embodiments of inventiveconcepts.

FIG. 10 is a timing diagram illustrating a supply cycle of process gasesfor forming a lower electrode according to some example embodiments ofinventive concepts.

FIG. 11 is a timing diagram illustrating a supply cycle of process gasesfor forming a dielectric layer according to some example embodiments ofinventive concepts.

FIG. 12 is a plan view illustrating a semiconductor memory deviceincluding a capacitor according to some example embodiments of inventiveconcepts.

FIGS. 13 to 19 are cross-sectional views taken along lines A1-A2 andB1-B2 of FIG. 12 to illustrate a method of manufacturing a semiconductormemory device including a capacitor, according to some exampleembodiments of inventive concepts.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

A semiconductor device and a method of manufacturing the same accordingto some example embodiments of inventive concepts will be describedhereinafter in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating a capacitor according tosome example embodiments of inventive concepts. FIG. 2 is an enlargedview of a region ‘Q’ of FIG. 1 . FIG. 3 is a plan view of a first layer.FIG. 4 is a plan view of a second layer. FIG. 5 is a plan view of athird layer. FIG. 6 is a plan view of a fourth layer.

Referring to FIGS. 1 and 2 , a capacitor CAP may include a lowerelectrode 10, an upper electrode 50, and a dielectric layer 30 betweenthe lower and upper electrodes 10 and 50. The upper electrode 50 may bespaced apart from the lower electrode 10 in a Z direction. For example,the capacitor CAP may be provided on a substrate (not illustrated), thelower electrode 10 may be adjacent to the substrate, and the upperelectrode 50 may be spaced apart from the substrate with the lowerelectrode 10 interposed therebetween. For example, the lower electrode10, the dielectric layer 30 and the upper electrode 50 may besequentially stacked on the substrate in the Z direction. As usedherein, the X direction, the Y direction, and the Z direction maycorrespond to different directions relative to one another, and use ofthe X direction, the Y direction, and the Z direction does notnecessarily indicate a relation to a ground, e.g. to a flat surfacerelative to the earth. For example, the Z direction may extend in adirection perpendicular to, or parallel to, a flat surface relative tothe earth. As another example, the lower electrode 10 may be conformalto another surface, such as to a base electrode.

Referring to FIG. 2 , the lower electrode 10 may include a firstcompound including a first metal element M1, a second metal element M2,and at least one oxygen atom OA. For example, the lower electrode 10 maybe a ternary compound expressed by a chemical formula of ABO₃. Here, ‘A’may correspond to the first metal element M1, and ‘B’ may correspond tothe second metal element M2. The first compound may have a perovskitecrystal structure, for example a structure having two cations ofdifferent sizes (e.g. ‘A’ and ‘B’, along with an anion (e.g. O₃). Forexample, the first metal element M1 may be disposed at each of eightcorners of a unit cell, and the second metal element M2 may be disposedat a center of the unit cell. The oxygen atom OA may be disposed at eachof centers of six faces of the unit cell. A ratio of the first metalelement M1:the second metal element M2:the oxygen atom OA may be 1:1:3in the unit cell. The lower electrode 10 may have a ferromagneticproperty. A thickness of the lower electrode 10 may range from about 50Å (5 nm) to about 100 Å (10 nm).

The lower electrode 10 may include atomic layers such as a first layerL1 and a second layer L2 which are alternately and repeatedly stacked inthe Z direction. As illustrated in FIG. 3 , the first layer L1 may beparallel to an XY plane and may be formed of the first metal element M1and the oxygen atom OA. The first layer L1 may correspond to a {100}plane of the lower electrode 10. The first metal element M1 may bedisposed at each of lattice points, and the oxygen atom OA may bedisposed at a center of a face of the unit cell which is formed by fourfirst metal elements M1. A ratio of the first metal element M1 to theoxygen atom OA in the first layer L1 may be 1:1.

As illustrated in FIG. 4 , the second layer L2 may be parallel to the XYplane and may be formed of the second metal element M2 and the oxygenatom OA. The second layer L2 may correspond to the {100} plane of thelower electrode 10. The second metal element M2 may be disposed at thecenter of the unit cell. The oxygen atom OA may be disposed at each ofthe centers of the faces included in/constituting/corresponding to theunit cell (or at each of centers of edges of the unit cell in a planview). A ratio of the second metal element M2 to the oxygen atom OA inthe second layer L2 may be 1:2.

A work function of the second metal element M2 may be greater than thatof the first metal element M1. For example, the work function of thefirst metal element M1 may be less than 4 eV. The work function of thesecond metal element M2 may be greater than 4.5 eV and less than 6 eV.For example, the first metal element M1 may be at least one of Sr, Ba,La, or Ca. The second metal element M2 may be at least one of Ru, Mo,Ir, Co, or Ni. For example, the first compound may be, but not limitedto, SrRuO₃, SrCoO₃, SrMoO₃, CaRuO₃, BaRuO₃, or (Ba, Sr)RuO₃.

The dielectric layer 30 may include a second compound including a thirdmetal element M3, a fourth metal element M4, and an oxygen atom OA. Forexample, the dielectric layer 30 may be or include a ternary compoundexpressed by a chemical formula of CDO₃. Here, ‘C’ may correspond to thethird metal element M3, and ‘D’ may correspond to the fourth metalelement M4. The second compound may have the perovskite crystalstructure. For example, the third metal element M3 may be disposed ateach of eight corners of a unit cell, and the fourth metal element M4may be disposed at a center of the unit cell. The oxygen atom OA may bedisposed at each of centers of six faces of the unit cell. A ratio ofthe third metal element M3:the fourth metal element M4:the oxygen atomOA may be 1:1:3 in the unit cell. The dielectric layer 30 may have aparaelectric and/or a ferroelectric property. A thickness of thedielectric layer 30 may range from about 50 Å (5 nm) to about 100 Å (10nm).

The dielectric layer 30 may include a third layer L3 and a fourth layerL4 which are alternately and repeatedly stacked in the Z direction. Asillustrated in FIG. 5 , the third layer L3 may be parallel to the XYplane and may be formed of the third metal element M3 and the oxygenatom OA. The third layer L3 may correspond to a {100} plane of thedielectric layer 30. The third metal element M3 may be disposed at eachof lattice points, e.g. each of lattice points of a unit cell, and theoxygen atom OA may be disposed at a center of a face of the unit cellwhich is formed by four third metal elements M3. A ratio of the thirdmetal element M3 to the oxygen atom OA in the third layer L3 may be 1:1.

As illustrated in FIG. 6 , the fourth layer L4 may be parallel to the XYplane and may be formed of the fourth metal element M4 and the oxygenatom OA. The fourth layer L4 may correspond to the {100} plane of thedielectric layer 30. The fourth metal element M4 may be disposed at thecenter of the unit cell. The oxygen atom OA may be disposed at each ofthe centers of the faces included in/constituting/corresponding to theunit cell (or at each of centers of edges of the unit cell in a planview). A ratio of the fourth metal element M4 to the oxygen atom OA inthe fourth layer L4 may be 1:2.

A work function of the fourth metal element M4 may be greater than thatof the third metal element M3. For example, the work function of thethird metal element M3 may be less than 4 eV. The work function of thefourth metal element M4 may be greater than 4.0 eV and less than 4.5 eV.For example, the third metal element M3 may be at least one of Ba, Sr,or Ca. The fourth metal element M4 may be at least one of Ti, Zr, or Hf.For example, the second compound may be, but not limited to, BaTiO₃,(Ba,Sr)TiO₃(BST), SrTiO₃, (Ba,Sr)(Zr,Ti)O₃ (BSZTO), Sr(Zr,Ti)O₃ (SZTO),Ba(Zr,Ti)O₃ (BZTO), (Ba,Sr)ZrO₃ (BSZO), SrZrO₃, or BaZrO₃. Alternativelyor additionally, the third metal element M3 may be an element (e.g., Pb)of which a work function is greater than 4 eV and less than that of thefourth metal element M4. In this case, the second compound may be orinclude Pb(Zr,Ti)O₃ (PZT) or (Pb,La)(Zr,Ti)O₃ (PLZT).

A work function of the fourth layer L4 corresponding to an oxide layerof the fourth metal element M4 may be greater than a work function ofthe third layer L3 corresponding to an oxide layer of the third metalelement M3. For example, when the fourth layer L4 is TiO₂ and the thirdlayer L3 is SrO, the work function (about 6.33 eV) of the fourth layerL4 may be greater than the work function (about 3.18 eV) of the thirdlayer L3. For example, the work function of the fourth layer L4 mayrange from about 5.0 eV to about 6.5 eV.

The upper electrode 50 may include a metal layer including at least oneof a noble metal (e.g., Pt, Ir, or Ru), Ti, or W. In some exampleembodiments, the upper electrode 50 may be formed of the same ternarycompound as the lower electrode 10. In some example embodiments, theupper electrode 50 may include a heterogeneous semiconductor materialsuch as silicon-germanium.

An interface IF may exist between the lower electrode 10 and thedielectric layer 30. The interface IF may be or correspond to a regionin which a first contact surface CS1 corresponding to a top surface ofthe lower electrode 10 is in contact, e.g. in direct and/or atomiccontact, with a second contact surface CS2 corresponding to a bottomsurface of the dielectric layer 30. The first contact surface CS1 andthe second contact surface CS2 may be spaced apart from each other interms of a lattice but may be in contact with each other in terms of amacro scale.

The first contact surface CS1 of the lower electrode 10 may be the {100}plane. The first contact surface CS1 may be one of the first and secondlayers L1 and L2 having the greater work function. As illustrated inFIG. 2 , the first contact surface CS1 may be or correspond to thesecond layer L2. The second layer L2 may consist of (or consistessentially of, or include) the second metal element M2 and the oxygenatom OA and may be expressed by BO₂. The first layer L1 may consist of(or consist essentially of, or include) the first metal element M1 andthe oxygen atom OA and may be expressed by AO. A work function of anoxide (e.g., BO₂) of the second metal element M2 may be greater thanthat of an oxide (e.g., AO) of the first metal element M1.

For example, a work function of the second layer L2 corresponding to anoxide layer of the second metal element M2 may be greater than a workfunction of the first layer L1 corresponding to an oxide layer of thefirst metal element M1. For example, when the second layer L2 is RuO₂and the first layer L1 is SrO, the work function (about 5.16 eV) of thesecond layer L2 may be greater than the work function (about 2.55 eV) ofthe first layer L1. The second contact surface CS2 of the dielectriclayer 30 may be one, having a small work function, of the third andfourth layers L3 and L4. For example, the second contact surface CS2 maybe or correspond to the third layer L3.

FIG. 7 is a conceptual view illustrating an interface between a lowerelectrode and a dielectric layer according to a comparative example.Referring to FIG. 7 , a first contact surface CS1 of a lower electrode10 may be or correspond to the first layer L1 in the comparativeexample.

When the dielectric layer 30 is formed of the ternary compound havingthe perovskite crystal structure, a dielectric constant of thedielectric layer 30 may be increased as compared with a binary compoundsuch as ZrO₂. As a result, a capacitance of the capacitor may beincreased. If the lower electrode 10 is formed of a binary compound,crystallinity of the dielectric layer 30 may be reduced by latticemismatch between the lower electrode 10 and the dielectric layer 30formed of the ternary compound, and thus a dielectric constant of thedielectric layer 30 may be deteriorated. A work function of a ternarycompound dielectric layer may be less than that of a binary compounddielectric layer, and thus a conduction band offset (CBO) value betweenthe ternary compound dielectric layer and a lower electrode may be lessthan about 1.0 eV. Thus, a leakage current of a capacitor may beincreased. However, according to the some example embodiments ofinventive concepts, the first contact surface CS1 of the lower electrode10 may be the second layer L2 of which the work function is greater thanthat of the first layer L1, and thus a CBO value may be increased toabout 2.0 eV or more. As a result, a leakage current of the capacitoraccording to the some example embodiments of inventive concepts may bereduced as compared with the case in which the first contact surface CS1is the first layer L1 like the comparative example of FIG. 7 , and thusthe reliability of the semiconductor device may be improved.

FIG. 8 is a process flowchart illustrating a method of forming acapacitor, according to some example embodiments of inventive concepts.FIG. 9 is a conceptual view illustrating a deposition apparatus forforming layers according to some example embodiments of inventiveconcepts. FIG. 10 is a timing diagram illustrating a supply cycle ofprocess gases for forming a lower electrode according to some exampleembodiments of inventive concepts. FIG. 11 is a timing diagramillustrating a supply cycle of process gases for forming a dielectriclayer according to some example embodiments of inventive concepts.

Referring to FIGS. 8 and 9 , a deposition apparatus 1000 may include adeposition chamber 21. For example, the deposition apparatus 1000 may beor include an atomic layer deposition (ALD) apparatus. The depositionapparatus 1000 may also include a chuck/platen/stage 22 which isprovided in the deposition chamber 21 and upon which a substrate WF isloaded, and a shower head 23 which is used to supply gases such asreaction gases into the deposition chamber 21. The stage 22 may includea heater 25 therein to maintain the substrate WF at a desired and/orspecific temperature. High radio frequency (HRF) power 28 of 13.56 MHzand/or 27 MHz may be applied to the shower head 23 (and/or a topelectrode connected to the shower head 23) and the stage 22 may begrounded, and thus plasma may be formed between the shower head 23 andthe stage 22. In some example embodiments, when the plasma is formed,low radio frequency (LRF) power 29 of 5 MHz or less (e.g., 400 kHz to500 kHz) may be additionally applied to the shower head 23 and/or thetop electrode as desired/needed.

Process gases may be supplied into the deposition chamber 21 through theshower head 23. In some example embodiments, the shower head 23 may beconnected to a first metal element source 11, a second metal elementsource 12, a third metal element source 13, a fourth metal elementsource 14, and an oxygen source 16 through one or more of supply lines.A carrier gas supply unit 15 may be connected to the shower head 23. Thefirst metal element source 11, the second metal element source 12, thethird metal element source 13, the fourth metal element source 14 andthe oxygen source 16 may be supplied to the shower head 23 throughindividual supply lines separated from each other. Alternatively, atleast portions of the individual supply lines may overlap, e.g. becommon, with each other. The first to fourth metal element sources 11,12, 13 and 14 may be or include sources of different elements from eachother. Alternatively, when kinds of at least some of the first to fourthmetal elements described above are the same as each other, at least someof the first to fourth metal element sources 11, 12, 13 and 14 may besources of substantially the same element. For example, when the firstmetal element M1 is the same as the third metal element M3, the firstmetal element source 11 and the third metal element source 13 may besubstantially the same source.

A carrier gas supplied from the carrier gas supply unit 15 may carryanother source and/or a precursor into the deposition chamber 21. Thecarrier gas may enable purging of an unreacted material and/or reactionbyproducts in the deposition chamber 21 to the outside of the depositionchamber 21 through the use of a vacuum pump. The carrier gas may be orinclude an inert gas such as helium (He) or neon (Ne) and/or may be agas having very low reactivity, such as nitrogen (N₂) or carbon dioxide(CO₂). However, example embodiments of inventive concepts are notlimited thereto. At least a portion of a supply line of the carrier gassupply unit 15 may overlap with the supply lines of the first metalelement source 11, the second metal element source 12, the third metalelement source 13, the fourth metal element source 14 and the oxygensource 16. Alternatively, the supply line of the carrier gas supply unit15 may be separated from the supply lines of the first metal elementsource 11, the second metal element source 12, the third metal elementsource 13, the fourth metal element source 14 and the oxygen source 16.

A substrate WF may be loaded on the stage 22 in the deposition chamber21 (S100). The substrate WF may be a wafer, such as a 200 mm or 300 mmdiameter wafer. A plurality of sources may be supplied into thedeposition chamber 21 to form a lower electrode on the substrate WF(S200). The process of forming the lower electrode may be completedafter the lower electrode is formed to have a specific and/or desiredthickness, and then, a first thermal treatment process may be performed(S300). The process of forming the lower electrode will be describedhereinafter in more detail.

Referring to FIGS. 1 to 4 and 8 to 10 , the lower electrode 10 may beformed on the substrate WF (e.g., the wafer) (S200). The formation ofthe lower electrode 10 may be performed like and/or according to thetiming diagram of FIG. 10 . The formation of the lower electrode 10 mayinclude a plurality of first cycles CL1. The first cycle CL1 may includea process SC1 of forming the first layer L1 (hereinafter, referred to asa first process SC1) and a process SC2 of forming the second layer L2(hereinafter, referred to as a second process SC2).

The first process SC1 may include a process S101 of supplying the firstmetal element source 11, a first purge process P1, a first supplyingprocess S102 of the oxygen source 16, and a second purge process P2,which are sequentially performed. The first layer L1 which consists of(or consists essentially of, or includes) the first metal element M1(such as in a gaseous-phase) and the oxygen atom OA and substantiallycorresponds to an (atomic) monolayer may be formed by the first processSC1. As disclosed herein, a monolayer may mean a layer having astructure in which atoms are two-dimensionally arranged. The secondprocess SC2 may include a process S103 of supplying the second metalelement source 12, a third purge process P3, a second supplying processS104 of the oxygen source 16, and a fourth purge process P4, which aresequentially performed. The second layer L2 which consists of (orconsists essentially of, or includes) the second metal element M2 andthe oxygen atom OA and substantially corresponds to an (atomic)monolayer may be formed by the second process SC2. A source gas notreacting with the wafer in the process immediately before each of thefirst to fourth purge processes P1, P2, P3 and P4 may be exhausted tothe outside of the deposition chamber 21 by each of or at least some ofthe first to fourth purge processes P1, P2, P3 and P4. The first cycleCL1 may be performed a plurality of times to form the lower electrode 10in which the first layer L1 and the second layer L2 are alternately andrepeatedly stacked.

The first metal element source 11 may include at least one of Sr, Ba,La, or Ca. For example, the first metal element source 11 may be astrontium (Sr) source. The strontium source may include acyclopenta-based ligand and/or a ketoimine-based ligand. The secondmetal element source 12 may include at least one of Ru, Mo, Ir, Co, orNi. For example, the second metal element source 12 may be a ruthenium(Ru) source. The ruthenium source may include a β-diketonate-basedligand. For example, the oxygen source 16 may include O₂ and/or O₃.

In the first process SC1, the process S101 of supplying the first metalelement source 11 may be performed for a time t01. For example, the timet01 may range from about 7 seconds to about 15 seconds. In the secondprocess SC2, the process S103 of supplying the second metal elementsource 12 may be performed for a time t03. For example, the time t03 mayrange from about 3 seconds to about 7 seconds. For example, the processS101 of supplying the first metal element source 11 may be longer thanthe process S103 of supplying the second metal element source 12. Eachof the first to fourth purge processes P1, P2, P3 and P4 may beperformed for a time of about 15 seconds to about 25 seconds. The firstsupplying process S102 of the oxygen source 16 may be performed for atime t02. For example, the time t02 may range from about 15 seconds toabout 25 seconds. The second supplying process S104 of the oxygen source16 may be performed for a time t04. For example, the time t04 may rangefrom about 15 seconds to about 25 seconds. During the first cycle CL1for forming the lower electrode 10, a chamber temperature may bemaintained at a temperature of about 300 degrees Celsius to about 500degrees Celsius. During the first cycle CL1 for forming the lowerelectrode 10, a pressure in the chamber may range from about 1 Torr (133Pascal) to about 3 Torr (400 Pascal).

The formation of the lower electrode 10 may be started at a start pointts1 of an initial first cycle CL1 s and may be ended at an end point te1of the last first cycle CL1 e. The initial first cycle CL1 s includingthe start point ts1 is started from the first process SC1 of the firstand second processes SC1 and SC2 in FIG. 10 . Alternatively, the initialfirst cycle CL1 s may be started from the second process SC2. In thelast first cycle CL1 e including the end point te1, a last suppliedmetal element source may be the second metal element source 12. Forexample, the last first cycle CL1 e may be ended by the second processSC2 of the first and second processes SC1 and SC2. As a result, thefirst contact surface CS1 of the lower electrode described withreference to FIGS. 1 and 2 may be or correspond to the second layer L2.

After the end point te1, the first thermal treatment process (S300) maybe performed. The first thermal treatment process (S300) may beperformed in-situ in the deposition chamber 21. However, some exampleembodiments of inventive concepts are not limited thereto; for example,the substrate WF may be thermally treated in another chamber. The metalelement sources may not be supplied during the first thermal treatmentprocess (S300). The first thermal treatment process (S300) may beperformed at a temperature of about 300 degrees Celsius to about 600degrees Celsius. A crystallinity of the lower electrode 10 may beincreased by the first thermal treatment process (S300).

The dielectric layer 30 may be formed on the lower electrode 10 (S400).The formation of the dielectric layer 30 may be performed like or in amanner corresponding to the timing diagram of FIG. 11 . The formation ofthe dielectric layer 30 may include a plurality of second cycles CL2.The second cycle CL2 may include a process SC3 of forming the thirdlayer L3 (hereinafter, referred to as a third process SC3) and a processSC4 of forming the fourth layer L4 (hereinafter, referred to as a fourthprocess SC4).

The third process SC3 may include a process S201 of supplying the thirdmetal element source 13, a fifth purge process P5, a third supplyingprocess S202 of the oxygen source 16, and a sixth purge process P6,which are sequentially performed. The third layer L3 which consists of(or consists essentially of, or includes) the third metal element M3 andthe oxygen atom OA and substantially corresponds to a monolayer may beformed by the third process SC3. The fourth process SC4 may include aprocess S203 of supplying the fourth metal element source 14, a seventhpurge process P7, a fourth supplying process S204 of the oxygen source16, and an eighth purge process P8, which are sequentially performed.The fourth layer L4 which consists of (or consists essentially of, orincludes) the fourth metal element M4 and the oxygen atom OA andcorresponds to substantially a monolayer may be formed by the fourthprocess SC4. The second cycle CL2 may be performed a plurality of timesto form the dielectric layer 30 in which the third layer L3 and thefourth layer L4 are alternately and repeatedly stacked. The third metalelement source 13 may include at least one of Sr, Ba, La, or Ca. Thefourth metal element source 14 may include at least one of Ti, Zr, orHf. For example, the fourth metal element source 14 may include TiCl₄.

In the third process SC3, the process S201 of supplying the third metalelement source 13 may be performed for a time t05. For example, the timet05 may range from about 7 seconds to about 15 seconds. In the fourthprocess SC4, the process S203 of supplying the fourth metal elementsource 14 may be performed for a time t07. For example, the time t07 mayrange from about 3 seconds to about 7 seconds. In other words, theprocess S201 of supplying the third metal element source 13 may belonger than the process S203 of supplying the fourth metal elementsource 14. Each of the fifth to eighth purge processes P5, P6, P7 and P8may be performed for a time of about 15 seconds to about 25 seconds. Thethird supplying process S202 of the oxygen source 16 may be performedfor a time t06. For example, the time t06 may range from about 15seconds to about 25 seconds. The fourth supplying process S204 of theoxygen source 16 may be performed for a time t08. For example, the timet08 may range from about 15 seconds to about 25 seconds. During thesecond cycle CL2 for forming the dielectric layer 30, a chambertemperature may be maintained at a temperature of about 300 degreesCelsius to about 500 degrees Celsius. During the second cycle CL2 forforming the dielectric layer 30, a pressure in the chamber may rangefrom about 1 Torr (133 Pascal) to about 3 Torr (400 Pascal).

The formation of the dielectric layer 30 may be started at a start pointts2 of an initial second cycle CL2 s and may be ended at an end point ofthe last second cycle. The initial second cycle CL2 s including thestart point ts2 may be started by the third process SC3 of the third andfourth processes SC3 and SC4. For example, in the initial second cycleCL2 s including the start point ts2, an initially supplied metal elementsource may be the third metal element source 13. As a result, the secondcontact surface CS2 of the dielectric layer 30 described with referenceto FIGS. 1 and 2 may be or correspond to the third layer L3.Alternatively, the initial second cycle CL2 s including the start pointts2 may be started from the fourth process SC4 of the third and fourthprocesses SC3 and SC4. As a result, the second contact surface CS2 maybe or correspond to the fourth layer L4.

After the formation of the dielectric layer 30 is completed, a secondthermal treatment process (S500) may be performed. The second thermaltreatment process (S500) may be performed in-situ in the depositionchamber 21. However, some example embodiments of inventive concepts arenot limited thereto. The metal element sources may not be suppliedduring the second thermal treatment process (S500). The second thermaltreatment process (S500) may be performed at a temperature of about 300degrees Celsius to about 600 degrees Celsius. Alternatively, the secondthermal treatment process (S500) may be omitted. Thereafter, a processof forming the upper electrode 50 may be performed.

FIG. 12 is a plan view illustrating a semiconductor memory deviceincluding a capacitor according to some example embodiments of inventiveconcepts. FIGS. 13 to 19 are cross-sectional views taken along linesA1-A2 and B1-B2 of FIG. 12 to illustrate a method of manufacturing asemiconductor memory device including a capacitor, according to someexample embodiments of inventive concepts.

In the following example embodiments, the capacitor used as a storageportion of a semiconductor memory device will be described as anexample. However, the capacitor according to some example embodiments ofinventive concepts is not limited to the storage portion of thesemiconductor memory device but may be used as a non-memory element suchas a decoupling structure.

Referring to FIGS. 12 and 13 , a device isolation pattern 302 may bedisposed in a substrate 301 to define active portions ACT. The substrate301 may be or include a semiconductor substrate, such as asingle-crystal silicon wafer that has been lightly doped, e.g. lightlydoped with boron. Each of the active portions ACT may have an isolatedshape when viewed in a plan view. Each of the active portions ACT mayhave a bar shape extending in a third direction D3 when viewed in a planview. Each of the active portions ACT may correspond to a portion of thesubstrate 301, which is surrounded by the device isolation pattern 302when viewed in a plan view.

Word lines WL may intersect the active portions ACT. The word lines WLmay be respectively disposed in grooves formed in the device isolationpattern 302 and the active portions ACT. The word lines WL may beparallel to a first direction D1 intersecting the third direction D3.The word lines WL may include a conductive material. A gate dielectriclayer 307 may be disposed between the word line WL and an inner surfaceof the groove. The gate dielectric layer 307 may include at least one ofa thermal oxide, silicon nitride, silicon oxynitride, or a high-kdielectric material.

A first dopant region 312 a may be disposed in each of the activeportions ACT between a pair of the word lines WL, and a pair of seconddopant regions 312 b may be disposed in both edge regions of each of theactive portions ACT, respectively. The first and second dopant regions312 a and 312 b may be doped with, for example, N-type dopants such asphosphorus and/or arsenic. The first dopant region 312 a may correspondto a common drain region, and the second dopant regions 312 b maycorrespond to source regions. Each of the word lines WL and the firstand second dopant regions 312 a and 312 b adjacent thereto mayconstitute (e.g. correspond to) a transistor, and may act as, functionas, or correspond to an access transistor for accessing a storageelement of a DRAM cell; however, example embodiments are not limitedthereto.

Top surfaces of the word lines WL may be lower than top surfaces of theactive portions ACT. A word line capping pattern 310 may be disposed oneach of the word lines WL. The word line capping patterns 310 may haveline shapes extending in a longitudinal direction of the word lines WLand may cover the top surfaces of the word lines WL. The word linecapping patterns 310 may include, for example, silicon nitride.

An interlayer insulating pattern 305 may be disposed on the substrate301. The interlayer insulating pattern 305 may be formed of a single ormulti-layer including at least one of a silicon oxide layer, a siliconnitride layer, or a silicon oxynitride layer.

Upper portions of the substrate 301, the device isolation pattern 302and the word line capping pattern 310 may be partially recessed to forma first recess region R1. Bit lines BL may be disposed on the interlayerinsulating pattern 305. The bit lines BL may intersect the word linecapping patterns 310 and the word lines WL. As illustrated in FIG. 12 ,the bit lines BL may extend in a second direction D2 intersecting thefirst and third directions D1 and D3. Each of the bit lines BL mayinclude a poly-silicon pattern 330, an ohmic pattern 331, and ametal-containing pattern 332, which are sequentially stacked. Thepoly-silicon pattern 330 may include poly-silicon doped or not dopedwith dopants. The ohmic pattern 331 may include a metal silicide. Themetal-containing pattern 332 may include at least one of a metal (e.g.,tungsten, titanium, and/or tantalum) or a conductive metal nitride(e.g., titanium nitride, tantalum nitride, and/or tungsten nitride). Abit line capping pattern 337 may be disposed on each of the bit linesBL. The bit line capping pattern 337 may include an insulating materialsuch as silicon nitride. The bit line capping patterns 337 may includethe same, or different materials from that of the word line cappingpatterns 310.

A bit line contact DC may be disposed in the first recess region R1intersecting the bit line BL. The bit line contact DC may includepoly-silicon doped or not doped with dopants, such as boron. The bitline contact DC may be electrically connected to the first dopant region312 a and may electrically connect the first dopant region 312 a to thebit line BL.

A filling insulation pattern 341 may be disposed in the first recessregion R1 in which the bit line contact DC is not disposed. The fillinginsulation pattern 341 may have a single-layered or multi-layeredstructure including at least one of a silicon oxide layer, a siliconnitride layer, or a silicon oxynitride layer.

Storage node contacts BC may be disposed between a pair of the bit linesBL adjacent to each other, as illustrated in FIG. 12 . The storage nodecontacts BC may be spaced apart from each other. The storage nodecontacts BC may include poly-silicon doped (e.g. doped with boron) ornot doped with dopants.

A bit line spacer including first and second spacers 321 and 325 spacedapart from each other by an air gap AG may be disposed between the bitline BL and the storage node contact BC. The first spacer 321 may covera sidewall of the bit line BL and a sidewall of the bit line cappingpattern 337. The second spacer 325 may be adjacent to the storage nodecontact BC. The first spacer 321 may extend to cover a sidewall of thebit line contact DC and a sidewall and a bottom surface of the firstrecess region R1. The first spacer 321 and the second spacer 325 mayinclude the same material. For example, the first spacer 321 and thesecond spacer 325 may include silicon nitride. Alternatively, the airgap AG may not be provided, but a third spacer may be provided betweenthe first spacer 321 and the second spacer 325.

A storage node ohmic layer 309 may be disposed on the storage nodecontact BC. The storage node ohmic layer 309 may include a metalsilicide, such as tungsten silicide (WSi_(x)). A diffusion barrierpattern 311 a may cover the storage node ohmic layer 309, the first andsecond spacers 321 and 325, and the bit line capping pattern 337. Thediffusion barrier pattern 311 a may include a metal nitride such astitanium nitride and/or tantalum nitride. A landing pad LP may bedisposed on the diffusion barrier pattern 311 a. The landing pad LP mayinclude a metal-containing material such as tungsten. An upper portionof the landing pad LP may cover a top surface of the bit line cappingpattern 337 and may have a width greater than that of the storage nodecontact BC. A center of the landing pad LP may be shifted from a centerof the storage node contact BC in the first direction D1, as illustratedin FIG. 12 . One upper sidewall of the bit line capping pattern 337 mayoverlap with the landing pad LP and may be covered with a third spacer327. A second recess region R2 may be formed at another upper sidewallof the bit line capping pattern 337.

A first capping pattern 358 a may be provided between adjacent landingpads LP. The first capping pattern 358 a may have a liner shape, and aspace surrounded thereby may be filled with a second capping pattern 360a. Each of the first and second capping patterns 358 a and 360 a mayinclude a silicon nitride layer, a silicon oxide layer, a siliconoxynitride layer, and/or a porous layer. The first capping pattern 358 aand the second capping pattern 360 a may fill the second recess regionR2.

An etch stop layer 370 may be formed on the landing pads LP, the firstcapping pattern 358 a and the second capping pattern 360 a. A first moldlayer 372, a support layer 374 and a second mold layer 376 may be formedon the etch stop layer 370. For example, each of the etch stop layer 370and the support layer 374 may be formed of a silicon nitride layer. Eachof the first and second mold layers 372 and 376 may be formed of amaterial having an etch selectivity with respect to the support layer374. For example, each of the first and second mold layers 372 and 376may be formed of a silicon oxide layer.

Referring to FIGS. 12 and 14 , the second mold layer 376, the supportlayer 374, the first mold layer 372 and the etch stop layer 370 may besequentially patterned to form electrode holes EH exposing the landingpads LP, respectively. A conductive layer may be formed to fill theelectrode holes EH, and an etch-back process and/or a chemicalmechanical polishing (CMP) process may be performed on the conductivelayer to remove the conductive layer disposed on the second mold layer376 and to form base electrodes SE in the electrode holes EH,respectively. The base electrode SE may include a metal nitride. Forexample, the base electrode SE may have a single-layered ormulti-layered structure including at least one of TiN, WN, TaN, HfN,ZrN, TiAlN, TaSiN, TiSiN, TaAlN, TiBN, TiON, TiAlON, TiCN, TiAlCN, orTiSiCN.

A third mask pattern 378 may be formed on the second mold layer 376. Thethird mask pattern 378 may have a plurality of openings 378 h. Each ofthe openings 378 h may expose top surfaces of the base electrodes SEadjacent to each other and the second mold layer 376 between the baseelectrodes SE.

Referring to FIGS. 12 and 15 , an anisotropic etching process (such as adry etching process) may be performed using the third mask pattern 378as an etch mask to remove the second mold layer 376 exposed by theopening 378 h and the support layer 374 thereunder. Thus, a supportpattern 374 a may be formed, and the first mold layer 372 under theopening 378 h may be exposed.

Referring to FIGS. 12 and 16 , the third mask pattern 378 may be removedto expose the second mold layer 376. The first and second mold layers372 and 376 may be removed by an isotropic etching process to exposesurfaces of the base electrode SE, the support pattern 374 a and theetch stop layer 370.

Referring to FIGS. 12 and 17 , lower electrodes 10 may be formed onexposed surfaces of the base electrodes SE. The lower electrodes 10 onthe base electrodes SE may be separated from each other. For example,the process of forming the lower electrodes 10 may include a process ofremoving portions deposited between the base electrodes SE to expose theetch stop layer 370. The lower electrodes 10 may cover sidewalls and topsurfaces of the base electrodes SE. The lower electrodes 10 may besubstantially the same as the lower electrode 10 described withreference to FIGS. 1 to 11 and may be formed by substantially the samemethod as the lower electrode 10 of FIGS. 1 to 11 . Referring to FIG. 17, the lower electrode 10 may be conformal to a shape of the baseelectrode SE; for example, the lower electrode 10 may be deposited in amanner to follow the shape of the base electrode SE.

Referring to FIGS. 12 and 18 , a dielectric layer 30 may be formed tocover the lower electrodes 10. The dielectric layer 30 may cover aplurality of the lower electrodes 10 in common. The dielectric layer 30may be substantially the same as the dielectric layer 30 described withreference to FIGS. 1 to 11 and may be formed by substantially the samemethod as the dielectric layer 30 of FIGS. 1 to 11 . Referring to FIG.16 , the dielectric layer 30 may be conformal to a shape of the lowerelectrode 10; for example, the dielectric layer 30 may be deposited in amanner to follow the shape of the lower electrode 10.

Referring to FIGS. 12 and 19 , an upper electrode 50 may be formed onthe dielectric layer 30. The upper electrode 50 may be substantially thesame as the upper electrode 50 described with reference to FIGS. 1 to 11and may be formed by substantially the same method as the upperelectrode 50 of FIGS. 1 to 11 . Referring to FIG. 19 , the upperelectrode may be conformal to a shape of the dielectric 30 and/or mayentirely fill the openings. A semiconductor memory device having acapacitor CAP including the base electrode SE, the lower electrode 10,the dielectric layer 30 and the upper electrode 50 may be formed by theformation of the upper electrode 50. Other processes (not illustrated)may include planarization of the top surfaces of the upper electrode 50,e.g. planarization by etch-back and/or CMP processes. The capacitor CAPmay act as, function as, or correspond to a storage element for a DRAMcell; however, example embodiments are not limited thereto.

According to the some example embodiments of inventive concepts, thecontact surface of the lower electrode, which is in contact with thedielectric layer, may be controlled to reduce a leakage current of thesemiconductor device and to improve the reliability of the semiconductordevice.

While inventive concepts have been described with reference to exampleembodiments, it will be apparent to those of ordinary skill in the artthat various changes and modifications may be made without departingfrom the spirits and scopes of the inventive concepts. Therefore, itshould be understood that the above embodiments are not limiting, butillustrative. Thus, the scopes of inventive concepts are to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing description.

What is claimed is:
 1. A semiconductor device comprising a capacitor ona substrate, the capacitor including a first electrode, a dielectriclayer, and an second electrode sequentially stacked on the substrate,wherein the first electrode has a pillar shape; the first electrodeincludes ABO₃ where ‘A’ is a first metal element and ‘B’ is a secondmetal element having a work function greater than that of the firstmetal element; the dielectric layer includes CDO₃ where ‘C’ is a thirdmetal element and ‘D’ is a fourth metal element; the first electrodeincludes a first layer and a second layer which are alternately andrepeatedly stacked; the first layer includes the first metal element andoxygen; the second layer includes the second metal element and oxygen;and the dielectric layer is in contact with the first electrode at afirst contact surface, the first contact surface corresponding to thesecond layer.
 2. The semiconductor device of claim 1, further comprises,a first conductive line buried in an upper portion of the substrate, thefirst conductive line extending in a first direction; an active portionin the upper portion of the substrate, the active portion defined by adevice isolation pattern, the active portion including a first dopantregion and a second dopant region which are separated from each otherwith the first conductive line interposed between the first dopantregion and the second dopant region; a second conductive line on thesubstrate, the second conductive line extending in a second directionintersecting the first direction, the second conductive line connectedto the first dopant region; a contact connected to the second dopantregion.
 3. The semiconductor device of claim 1, wherein the firstcontact surface has a {100} crystal plane.
 4. The semiconductor deviceof claim 1, wherein each of the first electrode and the dielectric layerhave a perovskite crystal structure.
 5. The semiconductor device ofclaim 1, wherein the dielectric layer includes a third layer and afourth layer which are alternately and repeatedly stacked; the thirdlayer includes the third metal element and oxygen; the fourth layerincludes the fourth metal element and oxygen; and the dielectric layeris in contact with the first electrode at a second contact surface, thesecond contact surface corresponding to the third layer.
 6. Thesemiconductor device of claim 5, wherein a work function of the fourthmetal element is greater than a work function of the third metalelement.
 7. The semiconductor device of claim 1, wherein the workfunction of the second metal element is greater than a work function ofthe fourth metal element.
 8. The semiconductor device of claim 1,wherein the work function of the second metal element is greater than4.5 eV and less than 6 eV.
 9. The semiconductor device of claim 1,wherein the first metal element is at least one of Sr, Ba, La, or Ca.10. The semiconductor device of claim 1, wherein the second metalelement is at least one of Ru, Mo, Ir, Co, or Ni.
 11. The semiconductordevice of claim 1, wherein the third metal element is at least one ofBa, Sr, or Ca.
 12. The semiconductor device of claim 1, wherein thefourth metal element is at least one of Ti, Zr, or Hf.
 13. Thesemiconductor device of claim 1, wherein a thickness of the firstelectrode is between 50 Å to 100 Å.
 14. The semiconductor device ofclaim 1, wherein the first electrode comprises a base electrode and alower electrode; and the lower electrode covers a sidewall of the baseelectrode and a top surface of the base electrode.
 15. The semiconductordevice of claim 1, further comprises a support pattern supporting asidewall of the first electrode.
 16. A semiconductor device comprising acapacitor on a substrate, the capacitor including a first electrode, adielectric layer, and an second electrode sequentially stacked on thesubstrate, wherein the first electrode has a pillar shape; a top surfaceof the first electrode contacts a bottom surface of the dielectriclayer; the first electrode includes a first metal element, a secondmetal element, and oxygen; the dielectric layer includes a third metalelement, a fourth metal element, and oxygen, the first electrodeincludes a first layer and a second layer which are alternately andrepeatedly stacked; the first layer includes the first metal element andoxygen, and the second layer includes the second metal element andoxygen; the first metal element is at least one of Sr, Ba, La, or Ca,and the second metal element is at least one of Ru, Mo, Ir, Co, or Ni;and the dielectric layer contacts the first electrode at a first contactsurface, the first contact surface corresponding to the second layer.17. The semiconductor device of claim 16, wherein the dielectric layerincludes a third layer and a fourth layer which are alternately andrepeatedly stacked; the third layer includes the third metal element andoxygen; the fourth layer includes the fourth metal element and oxygen;and the dielectric layer contacts the first electrode at a secondcontact surface, the second contact surface corresponding to one of thethird layer or the fourth layer, the one of the third layer or thefourth layer having a smaller work function than the other of the thirdlayer or the fourth layer.
 18. The semiconductor device of claim 16,wherein the third metal element is at least one of Ba, Sr, or Ca; andthe fourth metal element is at least one of Ti, Zr, or Hf.
 19. Thesemiconductor device of claim 16, wherein the capacitor furthercomprises a base electrode; and the first electrode covers a sidewall ofthe base electrode and a top surface of the base electrode.
 20. Thesemiconductor device of claim 16, further comprises a support patternsupporting a sidewall of the first electrode.